I don't know if it makes sense to remove the file, AFAIK it is used in the simulation flow. Removing it from the bender.yml definitely makes sense though!

I don't know if it makes sense to remove the file, AFAIK it is used in the simulation flow. Removing it from the bender.yml definitely makes sense though!

My point is that if we remove it from bender we are also not using the file for simulations, is this correct? In addition, having SCM in the deps already allows the usage of register_file_1w_multi_port_read.sv but there is no module repetition. The two sv files are identical, the only difference is using tc_clk_gating/cluster_clk_gating for the gating cells. I can push the file back in the repo anyway

Of course, updating the testbench to work with bender would be best, but time investment would be needed.

hier-icache/SIM/compile.sh

Lines 36 to 37 in 3fcc6da

	vlog -quiet -sv ../RTL/L1_CACHE/register_file_1w_multi_port_read.sv
	vlog -quiet -sv ../RTL/L1_CACHE/register_file_1w_multi_port_read_test_wrap.sv

This is my main concern, ensuring that the testbench will still function correctly. I see two options: 1. keep the file in the repository currently, or 2. adjust the above lines accordingly.

Of course, updating the testbench to work with bender would be best, but time investment would be needed.

I got it and I perfectly agree on point 1

hier-icache/SIM/compile.sh

Lines 36 to 37 in 3fcc6da

	vlog -quiet -sv ../RTL/L1_CACHE/register_file_1w_multi_port_read.sv
	vlog -quiet -sv ../RTL/L1_CACHE/register_file_1w_multi_port_read_test_wrap.sv

This is my main concern, ensuring that the testbench will still function correctly. I see two options: 1. keep the file in the repository currently, or 2. adjust the above lines accordingly.
Of course, updating the testbench to work with bender would be best, but time investment would be needed.

I got it and I perfectly agree on point 1

It should be better now